ABORT信号(bus error)に関する調査 その２

 ABORT信号についてもう少し調べてみました。 

 DCJ11 Microprocessor User's Guide (EK-DCJ11-UG-PRE)の2-6,7には以下の記述があります。(色を変えたのは私が着目した部分です。)

 ABORT can also be asserted by external logic in the event of
conditions as a bus timeout, non-existent memory reference, parity
error, etc. External logic must ensure that: (1) the cycle is
stretched and that ABORT is asserted during the stretched portion
(i.e., when SCTL is asserted) and (2) ABORT is not asserted during
a non-I/O cycle.

また、 3-6には以下の記述があります。

 A stretched cycle lasts at least eight clock periods. A cycle is stretched in increments of two clock periods (T4) and is ended by the assertion of CONT.
If an internally generated abort condition such as an MMU error or address error exists, the DCJ11 asserts ABORT during the first part of the cycle. If this type of abort occurs, the DAL, BS, and MAP information should be ignored for the remainder of the cycle. If an abort is externally generated (such as bus timeout, non-existent memory reference, etc.), it must occur during the stretched portion of the cycle.

上記の記述から、bus timeoutによるABORT信号は、CONT信号によってstretched cycleが終了するまで保持されなければならないと考えました。この考えが正しいとすると、現在のABORT信号の振る舞いは仕様書の記述に適合していないと言えそうです。